1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having memory macros and logic cores on board and particularly to System on Chip (SoC) technology.
2. Description of Related Art
The SoC technology which integrates multiple functions in one chip has been widely researched and developed. The SoC has memory macros and logic cores on board, which are normally arranged in a dispersed manner. Use of Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM) for the memory macro is proposed. For example, Japanese Unexamined Patent Publication No. 2001-110197 discloses a semiconductor memory device composed of a SRAM macro. Further, Japanese Unexamined Patent Publications No. 10-189889 and 2001-101900 disclose a DRAM macro.
SRAM is normally composed of either four or six transistors per cell. A high resistance load cell has four transistors consisting of two selection transistors connected to a bit line pair and two transistors with a cross-connected gate and drain. An active device load has six transistors. On the other hand, DRAM is composed of one transistor and one capacitor.
Thus, DRAM is preferable than SRAM in terms of a chip area, power consumption, and costs. However, since DRAM requires refresh cycles and bit line precharge, SRAM is generally used for memory macros.
Though SoC generally uses SRAM as a memory macro for the above reason, reduction of a chip area is strongly required with an increase in the circuit size of SoC. If a memory macro is made of SRAM, for example, it occupies several tens of Mbit in SoC, and its effect is not negligible. Especially, the percentage of a memory in SoC increases recently and its effect is significant.
Further, with an increase in a circuit size, soft errors such as data breakdown due to alpha radiation and cosmic radiation grow into a serious problem.
The present invention has recognized that merely replacing SRAM with DRAM results in failure to read data during a refresh cycle. Further, though use of DRAM simplifies the configuration of a cell, it requires a complicated circuit for refresh control, and placing a refresh control circuit for each of dispersed memories lowers the effectiveness of chip area reduction.